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NCP1201 PWM Current-Mode Controller for Universal Off-Line Supplies Featuring Low Standby Power with Fault Protection Modes
Housed in SOIC-8 or PDIP-8 package, the NCP1201 enhances the previous NCP1200 series by offering a reduced optocoupler current with additional Brownout Detection Protection (BOK). Similarly, the circuit allows the implementation of complete off-line AC-DC adapters, battery chargers or Switchmode Power Supplies (SMPS) where standby power is a key parameter. The NCP1201 features efficient protection circuitry. When in the presence of a fault (e.g. failed optocoupler, overcurrent condition, etc.) the control permanently disables the output pulses to avoid subsequent damage to the system. The IC only restarts when the user cycles the mains power supply. With the low power internal structure, operating at a fixed 60 or 100 kHz, the controller supplies itself from the high-voltage rail, avoiding the need of an auxiliary winding. This feature naturally eases the designer's task in battery charger applications. Finally, current-mode control provides an excellent audio-susceptibility and inherent pulse-by-pulse control. When the load current falls down to a pre-defined setpoint (VSKIP) value, e.g. the output power demand diminishes, the IC automatically enters the skip cycle mode and can provide excellent efficiency under light load conditions. The skip mode is designed to operate at relatively lower peak current so that acoustic noise that commonly takes place will not happen with NCP1201.
Features
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8 8 1 SOIC-8 D SUFFIX CASE 751 1 8 PDIP-8 P SUFFIX CASE 626 1 1 1201Py0 AWL YYWWG 201Dx ALYW G
8
x y y xx A L Y, YY W, WW G or G
= Device Code: 6 for 60 kHz 1 for 100 kHz = Device Code: 6 for 60 kHz 10 for 100 kHz = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
* * * * * * * * * * * * *
AC Line Brownout Detect Protection, BOK Function Latchoff Mode Fault Protection No Auxiliary Winding Operation Internal Output Short-Circuit Protection Extremely Low No-Load Standby Power Current-Mode with Skip-Cycle Capability Internal Overtemperature Shutdown Internal Leading Edge Blanking 250 mA Gate Peak Current Driving Capability Internally Fixed Switching Frequency at 60 or 100 kHz Built-in Frequency Jittering for EMI Reduction Direct Optocoupler Connection Pb-Free Packages are Available
PIN CONNECTIONS
BOK FB CS GND 1 2 3 4 (Top View) 8 7 6 5 HV NC VCC DRV
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet.
Typical Applications
* AC-DC Adapters * Offline Battery Chargers * Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
(c) Semiconductor Components Industries, LLC, 2006
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February, 2006 - Rev. 4
Publication Order Number: NCP1201/D
NCP1201
C3 R3 470 p 100 k 250 V 1.0 W * D2 U1 1 4 2 3 2 90X264 Vac 3 + C2 4.7 m 400 V + 4 NCP1201 Q1 MTD1N60E 5 6 1N4937 + C5 10 m + C6 10 m 8 1N5819 D1 T1
L1 470 mH 0.2 A
6.5 V, 600 mA L3 47 mH 1.0 A
R1 195.7 k
DF06S
+ -
BR1
1
C1 4.7 m 400 V
C7 1.0 n 250 VAC Y1 + C4 10 mF SFH6156-2 4 R2 4.3 k L2 470 mH 0.2 A * Please refer to the application information section. R4 2.7 0.5 W 1 2 3 U2 D3 5V1
Figure 1. Typical Application Example
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Iref BOK 1 + - 50 mA 10.5 V/12.5 V FB 2 Oscillator 60 or 100 kHz Clock + + CS 3 - 1.92 V - 80 K 1.07 V Output Skip Cycle Comparator + - 24 K Output Set Maximum 83% Duty Cycle Enable 6 Q Reset + - + Output - + - HV Current Source 7 NC
8
HV
VCC
Reset Reset TSD Startup Blanking
GND
4 20 k + - 57 k 25 k Vref
250 ns L.E.B.
+ - Output
5 250 mA Internal Regulator Vref
DRV
0.9 V Overload
Figure 2. Simplified Functional Block Diagram
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PIN FUNCTION DESCRIPTION
Pin No. 1 2 Pin Name BOK FB Function Bulk OK Description This pin detects the input line voltage by sensing the bulk capacitor, and disables the PWM when line voltage is lower than normal. Sets the Peak Current Setpoint By connecting an optocoupler to this pin, the peak current setpoint is adjusted according to the output power demand. Internal monitoring of this pin level triggers the fault management circuitry. This pin senses the primary inductor current and routes it to the internal comparator via an LEB circuit. - The driver's output to an external MOSFET. This pin is connected to an external bulk capacitor of typically 10 mF. This unconnected pin ensures adequate creepage distance between High Voltage pin to other pins. Connected to the high-voltage rail, this pin injects a constant current into the VCC capacitor. 3 4 5 6 7 8 CS GND DRV VCC NC HV Current Sense Input The IC Ground Driving Pulses Supplies the IC No Connection Generates the VCC from the Line
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Power Supply Voltage, Pin 6 Input/Output Pins Pins 1, 2, 3, 5
Symbol VCC VIO
Value
Unit V V V
-0.3, 16
-0.3, 6.5 500 100 178
Maximum Voltage on Pin 8 (HV) Thermal Resistance, Junction-to-Air, PDIP-8 Version Thermal Resistance, Junction-to-Air, SOIC Version Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range ESD Capability, HBM (All pins except VCC and HV pins) (Note 1) ESD Capability, Machine Model (All pins except VCC and HV pins) (Note 1)
VHV RqJA RqJA TJ TA Tstg - -
C/W C/W C C C kV V
-40 to +150 -25 to +125 -55 to +150 2.0 200
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) > 2.0 kV per JEDEC standard: JESD22-A114. Machine Model (MM) > 200 V per JEDEC standard: JESD22-A115. 2. Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = -25C to +125C,
VCC = 11 V unless otherwise noted) Characteristic DYNAMIC SELF-SUPPLY VCC Increasing Level at which the Current Source Turns-Off VCC Decreasing Level at which the Current Source Turns-On Internal IC Current Consumption, No Output Load on Pin 5 Internal IC Current Consumption, 1.0 nF Output Load on Pin 5 NCP1201P60, NCP1201D60 NCP1201P100, NCP1201D100 Internal IC Current Consumption, Latchoff Phase INTERNAL STARTUP CURRENT SOURCE High-Voltage Current Source at VCCON - 0.2 V High-Voltage Current Source at VCC = 0 V HV Pin Leakage Current @ 450 V, VCC Pin Connected to Ground OUTPUT SECTION Output Voltage Rise-Time (CL = 1.0 nF, 10 V Output) Output Voltage Fall-Time (CL = 1.0 nF, 10 V Output) Source Resistance (VDRV = ) Sink Resistance (VDRV = ) CURRENT SENSE SECTION (Pin 5 Unloaded) Input Bias Current @ 1.0 V Input Level on Pin 3 Maximum Current Sense Input Threshold Default Current Sense Threshold for Skip Cycle Operation Propagation Delay from Current Detection to Gate OFF State Leading Edge Blanking Duration OSCILLATOR SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 KW) Oscillation Frequency NCP1201P60, NCP1201D60 NCP1201P100, NCP1201D100 Built-in Frequency Jittering (as a function of Vcc voltage) NCP1201P60, NCP1201D60 NCP1201P100, NCP1201D100 Maximum Duty Cycle FEEDBACK SECTION (VCC = 11 V, Pin 5 Unloaded) Internal Pullup Resistor Feedback Pin to Pin 3 Current Setpoint Division Ratio BROWNOUT DETECT SECTION BOK Input Threshold Voltage BOK Input Bias Current (VBOK < Vth) Source Bias Current (Turn on After VBOK > Vth) FREQUENCY SKIP CYCLE SECTION Built-in Frequency Skip Cycle Comparator Voltage Threshold THERMAL SHUTDOWN Thermal Shutdown Trip Point, Temperature Rising (Note 3) Thermal Shutdown Hysteresis 3. Verified by design. TSD THYST - - 145 25 - - C C VSKIP 0.96 1.07 1.18 V Vth IIB-BOK ISC 1.75 - 40 1.92 11 50 2.05 100 58 V nA mA RUP Iratio 10 2.9 17 3.3 24 4.0 kW - Fjitter - - Dmax 74 493 822 83 - - 87 % FOSC 52 92 60 100 72 117 Hz/V kHz IIB-CS VILIMIT VILSKIP TDEL TLEB - 0.8 250 35 150 10 0.9 325 65 260 100 1.0 390 160 400 nA V mV ns ns Tr Tf ROH ROL - - 26 4.0 116 41 38 10 - - 60 22 ns ns W W IC1 IC2 ILEAK 3.6 7.5 - 5.3 11.1 30 7.1 15 70 mA mA mA VCCOFF VCCON ICC1 ICC2 0.75 1.6 ICC3 405 1.6 2.1 575 2.2 2.8 772 mA 11.5 9.6 440 12.5 10.5 905 13.5 11.3 1300 V V mA mA Symbol Min Typ Max Unit
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TYPICAL CHARACTERISTICS
VCCOFF, VCC OFF THRESHOLD VOLTAGE (V) VCCON, VCC ON THRESHOLD VOLTAGE (V) 12.9 12.7 12.5 12.3 12.1 11.9 11.7 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 10.8
10.6
10.4
10.2
10 9.8 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 3. VCC OFF Threshold Voltage vs. Junction Temperature
Figure 4. VCC ON Threshold Voltage vs. Junction Temperature
ICC2, CURRENT CONSUMPTION (mA)
1100 ICC1, CURRENT CONSUMPTION WITH NO LOAD (mA)
2.6 1 nF Load 2.4 2.2 2.0 1.8 1.6 1.4 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 60 KHz
1000
900
100 KHz
800
700 600 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 5. IC Current Consumption, ICC1 vs. Junction Temperature
Figure 6. IC Current Consumption, ICC2 vs. Junction Temperature
700 ICC3, IC CURRENT CONSUMPTION AT LATCHOFF PHASE (mA) IC1, HV PIN STARTUP CURRENT SOURCE (mA)
8.0 VCC = 11 V 6.5
600
5.0
500
3.5
400
2.0 0.5
300 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 7. IC Current Consumption at Latchoff Phase vs. Junction Temperature
Figure 8. HV Pin Startup Current Source vs. Junction Temperature
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TYPICAL CHARACTERISTICS
14 IC2, HV PIN STARTUP CURRENT SOURCE (mA) ILEAK, LEAKAGE CURRENT (mA) 125 80
12
60
10
40
8
20
6 VCC = 0 V 4 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
0 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 9. HV Pin Startup Current Source vs. Junction Temperature
Figure 10. Leakage Current vs. Junction Temperature
70 ROH, SOURCE RESISTANCE (W) ROL, SINK RESISTANCE (W) -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 60 50 40 30 20 10 0
20
16
12
8
4 0 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 11. Output Source Resistance vs. Junction Temperature
VILIMIT, MAXIMUM CURRENT SENSE THRESHOLD (V) IIB-CS, CS PIN INPUT BIAS CURRENT (nA)
Figure 12. Output Sink Resistance vs. Junction Temperature
12 11 10 9 8 7 6 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
1.00
0.96
0.92
0.88
0.84 0.80 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 13. CS Pin Input Bias Current @ 1.0 V vs. Junction Temperature
Figure 14. Maximum Current Sense Threshold vs. Junction Temperature
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TYPICAL CHARACTERISTICS
VILSKIP, DEFAULT CURRENT SENSE THRESHOLD FOR SKIP CYCLE (mV) 340 100 TDEL, PROPAGATION DELAY (nS) -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 85 70 55 40 25 10 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
330
320
310
300 290
Figure 15. Default Current Setpoint for Skip Cycle vs. Junction Temperature
400 TLEB, LEADING EDGE BLANKING DURATION (nS) 350 300 250 200 150 100 50 0 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 16. Propagation Delay from Current Detection to Gate Driver vs. Junction Temperature
FOSC, OSCILLATOR FREQUENCY (kHz) 120 100 KHz 100 80 60 KHz 60 40 20 0 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 17. Leading Edge Blanking Duration vs. Junction Temperature
Figure 18. Oscillator Frequency vs. Junction Temperature
1400 Fjitter, FREQUENCY JITTER (Hz/V) 1200 1000 800 600 60 KHz 400 200 0 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 100 KHz Dmax, MAXIMUM DUTY CYCLE (%)
85 84 83 82 81 80 79 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 19. Frequency Jittering vs. Junction Temperature
Figure 20. Maximum Duty Cycle vs. Junction Temperature
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TYPICAL CHARACTERISTICS
RUP, INTERNAL PULLUP RESISTOR (kW) 19 Iratio, FEEDBACK PIN TO PIN 3 CURRENT RATIO 18 17 16 15 14 13 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 3.40 3.35 3.30 3.25 3.20 3.15 3.10 3.05 3.00 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 21. FB Pin Pullup Resistor vs. Junction Temperature
Vth, BOK INPUT THRESHOLD VOLTAGE (V)
Figure 22. Feedback Pin to Pin 3 Current Setpoint Ratio vs. Junction Temperature
IIB-BOK, BOK INPUT BIAS CURRENT (nA)
2.00 1.95 1.90 1.85 1.80 1.75 1.70 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
12 11 10 9 8 7 VBOK < Vth 6 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 23. BOK Threshold Voltage vs. Junction Temperature
Figure 24. BOK Input Bias Current vs. Junction Temperature
51 50 49 48 47 46 VBOK < Vth 45 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 VSKIP, SKIP CYCLE COMPARATOR THRESHOLD VOLTAGE (V) ISC, BOK BIAS CURRENT (mA)
1.15
1.10
1.05
1.00
0.95 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 25. BOK Source Bias Current vs. Junction Temperature
Figure 26. Skip Mode Threshold Voltage vs. Junction Temperature
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DETAILED OPERATING DESCRIPTION Introduction The NCP1201 implements a standard current mode architecture where the switch-off time is dictated by the peak current setpoint. This component represents the ideal candidate where low part-count is the key criteria, particularly in low-cost AC-DC adapters, auxiliary supplies etc. Due to its high-performance High-Voltage technology, the NCP1201 incorporates all the necessary components normally needed in UC384X based supplies: timing components, feedback devices, low-pass filter and self-supply. This later point emphasizes the fact that ON Semiconductor's NCP1201 does NOT need an auxiliary winding to operate: the device is self supplied from the high-voltage rail and delivers a VCC to the IC. This system is named the Dynamic Self-Supply (DSS). Dynamic Self-Supply The DSS principle is based on the charge/discharge of the VCC bulk capacitor from a low level up to a higher level. We can easily describe the current source operation following simple logic equations: POWER-ON: IF VCC < VCCOFF THEN Current Source is ON, no output pulses IF VCC decreasing > VCCON THEN Current Source is OFF, output is pulsing IF VCC increasing < VCCOFF THEN Current Source is ON, output is pulsing Typical values are: VCCOFF = 12.5 V, VCCON = 10.5 V To better understand the operation principle, Figure 27 sketch offers the necessary explanation,
Vripple = 2 V
VCCOFF = 12.5 V VCC VCCON = 10.5 V ON
OFF
Current Source
Output Pulses 10 mS 30 mS 50 mS 70 mS 90 mS
Figure 27. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor
The DSS behavior actually depends on the internal IC consumption and the MOSFET's gate charge Qg. If we select a MOSFET like the MTP2N60E, Qg max equals 22 nC. With a maximum switching frequency of 70 kHz for the oscillator 60 kHz, the average power necessary to drive the MOSFET (excluding the driver efficiency and neglecting various voltage drops) is:
Pdriver + Fsw(max) Qg VCC
(eq. 1)
Where, Pdriver = Average Power to drive the MOSFET Fsw(max) = Maximum switching frequency Qg = MOSFET's gate charge VCC = VGS level applied to the gate of the MOSFET To obtain an estimation of the driving current, simply divide Pdriver by VCC,
Idriver + Fsw(max) Qg + 1.54 mA (eq. 2)
The total standby power consumption at no-load will therefore heavily rely on the internal IC current consumption plus the driving current (altered by the driver's efficiency). Suppose that the IC is supplied from a 350 VDC line. The current flowing through pin 8 is a direct image of the NCP1201 current consumption (neglecting the switching losses of the HV current source). If ICC2 equals 2.1 mA @ TA = 25C, then the power dissipated (lost) by the IC is simply: 350 V x 2.1 mA = 735 mW. For design and reliability reasons, it would be interesting to reduce this source of wasted power. In order to achieve that, different methods can be used. 1. Use a MOSFET with lower gate charge Qg; 2. Connect pin through a diode (1N4007 typically) to one of the mains input. The average value on pin 8 becomes:
VmainsPEAK p 2
(eq. 3)
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Our power contribution example drops to 223 V x 2.1 m = 468.3 mW. If a resistor is installed between the mains and the diode, you further force the dissipation to migrate from the package to the resistor. The resistor value should be carefully selected to account for low-line startup.
HV
1 Mains Cbulk 2 3 4
8 7 6 5
Figure 28. A Simple Diode Naturally Reduces the Average Voltage on Pin 8
Skipping Cycle Mode The NCP1201 automatically skips switching cycles when the output power demand drops below a preset level. This is accomplished by monitoring the FB pin. In normal operation, FB pin imposes a peak current according to the load value. If the load demand decreases, the internal loop asks for less peak current. When this set-point reaches the skip mode threshold level, 1.07 V, the IC prevents the current from decreasing further down and starts to blank the output pulses, i.e. the controller enters the so-called Skip Cycle Mode, also named Controlled Burst Operation. The power transfer now depends upon the width of the pulse bunches, Figure 29. Suppose we have the following component values: Lp, primary inductance = 1.0 mH Fsw, switching frequency = 60 kHz Ip (skip) = 200 mA (or 333 mV/Rsense) The theoretical power transfer is therefore:
1 2 Lp Ip2 Fsw + 1.2 W
(eq. 4)
3. Permanently force the VCC level above VCCOFF with an auxiliary winding. It will automatically disconnect the internal startup source and the IC will be fully self-supplied from this winding. Again, the total power drawn from the mains will significantly decrease. By using this approach, user need to make sure the auxiliary voltage never exceeds the 16 V limit for all line conditions.
If the controller enters Skip Cycle Mode with a pulse packet length of 20 ms over a recurrent period of 100 ms, then the total power transfer reduced to 1.2 W x 0.2 = 240 mW. To better understand how this Skip Cycle Mode takes place, a look at the operation mode versus the FB pin voltage level shown below, immediately gives the necessary insight.
FB
4.2 V, FB Pin Open 2.97 V, Upper Dynamic Range Normal Current Mode Operation
Skip Cycle Operation Ip(min) = 333 mV / Rsense
1.07 V
Figure 29. Feedback Pin Voltage and Modes of Operation
When FB pin voltage level is above the skip cycle threshold (1.07 V by default), the peak current cannot exceed 0.9 V/Rsense. When the IC enters the skip cycle mode, the
peak current cannot go below VSKIP/3.3. By using the peak current limit reduction scheme, the skip cycle takes place at a lower peak current, which guarantees noise free operation.
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P1 = 0.4 W
P2 = 1.8 W
P3 = 3.6 W
Figure 30. MOSFET VDS at Various Power Levels, P1300.0M
Max peak current
200.0M
Skip Cycle current limit
100.0M
0
315.4uS
882uS
1.450mS
2.017mS
2.585mS
Figure 31. The Skip Cycle Takes Place at Low Peak Current
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Brownout Detect Protection In order to avoid output voltage bouncing during electricity brownout, a Bulk Capacitor Voltage Comparator with programmable hysteresis is included in this device. The non-inverting input, pin 1, is connected to the voltage divider comprised of RUpper and RLower as shown in Figure 32, monitoring the bulk capacitor voltage level. The inverting input is connected to a threshold voltage of 1.92 V internally. As bulk capacitor voltage drops below the pre-programmed level, i.e. Pin 1 voltage drops below 1.92 V, a reset signal will be generated via internal protection logic to the PWM Latch to turn off the Power Switch immediately. At the same time, an internal current source controlled by the state of the comparator provides a mean to setup the voltage hysteresis through injecting current into RLower. The equations below (Equations 5 and 6) show the relationship between VBULK levels and the voltage divider network resistors. Equations for resistors selection are:
RUpper ) RLower + RLower + (VBULK_H * VBULK_L) 50 mA (eq. 5) VBULK VREF
RUpper 50 mA + 1.92 V RLower - UVLO
BOK
Figure 32. Brown-Out Protection Operation
[1.92 V(VBULK_H * VBULK_L)] (50 mA VBULK_H)
(eq. 6)
Assume VBULK_H = 90 Vdc and VBULK_L = 80 Vdc, by using 4.3 kW for RLower then RUpper is about 195.7 kW.
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APPLICATION INFORMATION Power Dissipation The NCP1201 can be directly supplied from the DC rail through the internal DSS circuitry. The average current flowing through the DSS is therefore the direct image of the NCP1201 current consumption. The total power dissipation can be evaluated using: (VHVDC * 11 V) ICC2. If the device operates on a 250 VAC rail, the maximum rectified voltage can go up to 350 VDC. At TA = 25C, ICC2 = 2.1 mA for the 60 kHz version over a 1.0 nF capacitive load. As a result, the NCP1201 will dissipate 350 V x 2.1 mA = 735 mW (TA = 25_C). The SOIC-8 package offers a junction-to-ambient thermal resistance RqJ-A of 178C/W. Adding some copper area around the device pins will help to improve this number, 12mm x 12mm copper can drop RqJ-A down to 100C/W with 35 m copper thickness (1 oz.) or 6.5mm x 6.5mm with 70 m copper thickness (2 oz.). With this later number, we can compute the maximum power dissipation the package accepts at an ambient of 50C:
P max + Tjmax-TAmax RqJ-A + 750 mW (TJmax = 125_C),
MOSFET's Qg which ICC2 ICC1 + Fsw x Qg. Final calculation should thus account for the total gate-charge Qg your MOSFET will exhibit. If the power estimation is beyond the limit, supply to the VCC with a series diode as suggested in Figure 28 can be used. As a result, it will drop the average input voltage and lower the dissipation to 350 V 2 1.6 mA + 356.5 mW. p Alternatively, an auxiliary winding can be used to disable the DSS and hence reduce the power consumption down to VCC x ICC2. By using the auxiliary winding supply method, the rectified auxiliary voltage should permanently stays above the VCCOFF threshold voltage, keeping DSS off and is safely kept well below the 16 V maximum rating for whole operating conditions. Non-Latching Shutdown In some cases, it might be desirable to shut off the device temporarily and authorize its restart once the control signal has disappeared. This option can easily be accomplished through a single NPN bipolar transistor wired between FB and ground. By pulling FB pin voltage below the VSKIP level, the output pulses are disabled as long as FB pin voltage is pulled below the skip mode threshold voltage. As soon as FB pin is released, the the device resumes its normal operation again. Figure 33 depicts an application example.
1 2 3 4 8 7 6 5
which is acceptable with our previous thermal budget. For the DIP8 package, adding a min-pad area of 80mm2 of 35 m copper (1 oz.), RqJ-A drops from 100C/W to about 75C/W. In the above calculations, ICC2 is based on a 1.0 nF output capacitor. As seen before, ICC2 will depend on your
ON/OFF
Q1
Figure 33. A Method to Shut Down the Device Without a Definitive Latchoff State
Fault Protection In applications where the output current is purposely not controlled (e.g. wall adapters delivering raw DC level), it is often required to permanently latchoff the power supply in presence of a fault. This fault can be either a short-circuit on the output or a broken optocoupler. In this later case, it is important to quickly react in order to avoid a lethal output voltage runaway. The NCP1201 includes a circuitry tailored to tackle both events. A short-circuit forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler LED. As a result, the FB pin level is pulled up to 4.2 V, as internally imposed by the IC. The peak current set-point goes to the maximum and the supply delivers a rather high power with all the associated effects. However, this can also happen in case of feedback loss, e.g. a broken optocoupler. To account for those
situations, NCP1201 included a dedicated overload protection circuitry. Once the protection activated, the circuitry permanently stops the pulses while the VCC moves between 10-12 V to maintain this latchoff state. The system resets when the user purposely cycles the VCC down below 3.0 V, e.g. when the power plug is removed from the mains. In NCP1201, the controller stops all output pulses as soon as the error flag is asserted, irrespective to the VCC level. However, to avoid false triggers during the startup sequence, NCP1201 purposely omits the very first VCC descent from 12 to 10 V. The error circuitry is actually armed just after this sequence, e.g. VCC crossing 10 V. Figure 34 details the timing sequence. The VCC capacitor should be calculated carefully to offer a sufficient time out during the first startup VCC descent.
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As shown below, the fault logic is armed once VCC crosses 10 V after startup phase. When powering the device from an auxiliary winding, meeting this condition can sometimes be problematic since upon startup, VCC naturally goes up and not down as with a DSS. As a result, VCC never crosses 10 V and the fault logic is not activated. If a short-circuit takes place, the fault circuitry activates as soon as VCC collapses below 10 V (because of the coupling between Vaux and
VCC Regulation occurs here 12 V 10 V No synchronization between DSS and fault event Time Drv Overload is not activated Overload is activated
Vout), but in presence of a broken optocoupler, i.e. feedback is open, VCC increases and the fault will never triggered! To avoid this problem, the application note "Tips and Tricks with NCP1200, AN8069/D" offers some possible solutions where the DSS is kept for protection logic operation only but all the driving power is derived from the auxiliary winding. Some solutions even offer the ability to disable the DSS in standby and benefit to low standby power.
Driver Pulses
Open-loop FB level
Latched-off Time
FB
Regulation Fault occurs here Time
Figure 34. Fault Protection Timing Diagram
Calculating the VCC Capacitor As the above section describes, the fall down sequence depends upon the VCC level, i.e. how long does it take for the VCC line to decrease from 12.5 V to 10.5 V. The required time depends on the powerup sequence of your system, i.e. when you first apply the power to the device. The corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 12.5 V to 10.5 V, otherwise the supply will not properly startup. The test consists in either simulating or measuring in the laboratory to determine time required for the system to reach the regulation at full load. Let's assume
that this time corresponds to 6.0 ms. Therefore a VCC fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. If the corresponding IC consumption, including the MOSFET drive, establishes at 1.8 mA for instance, we can calculate the required capacitor using the following formula: Dt + DV DV = 2.0 V. Then for a wanted Dt of 10 ms, C equals 9.0 mF or 10 mF for a standard value. When an overload condition occurs, the IC blocks its internal circuitry and its consumption drops to 575 mA typical. This explains the VCC falling slope changes after latchoff in Figure 34.
i C , with
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NCP1201
Protecting the Controller Against Negative Spikes As with any controller built upon a CMOS technology, it is the designer's duty to avoid the presence of negative spikes on sensitive pins. Negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. Sometimes, the injection can be so strong that internal parasitic SCRs are triggered, engendering irremediable damages to the IC if they are a low impedance path is offered between VCC and GND. If the current sense pin is often the seat of such spurious signals, the high-voltage pin can also be the source of problems in certain circumstances. During the turn-off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its VCC capacitor and keeps activating the MOSFET ON and OFF with a peak current limited by Rsense. Unfortunately, if the quality coefficient Q of the resonating network formed by Lp and Cbulk is low (e.g. the MOSFET Rdson + Rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. Since we are talking about ms pulses, the amount of injected charge (Q = I x t) immediately latches the controller which brutally discharges its VCC capacitor. If this VCC capacitor is of sufficient value, its stored energy damages the controller. Figure 35 depicts a typical negative shot occurring on the HV pin where the brutal VCC discharge testifies for latchup.
Figure 35. A negative spike takes place on the Bulk capacitor at the switch-off sequence
Simple and inexpensive cures exist to prevent from internal parasitic SCR activation. One of them consists in inserting a resistor in series with the high-voltage pin to keep the negative current to the lowest when the bulk becomes negative (Figure 36). Please note that the negative spike is clamped to -2 x Vf due to the diode bridge. Please refer to AND8069 for power dissipation calculations.
3 Rbulk > 4.7 k 2 + Cbulk 1 2 3 4 8 7 6 5 1+ CVCC
Another option (Figure 37) consists in wiring a diode from VCC to the bulk capacitor to force VCC to reach UVLOlow sooner and thus stops the switching activity before the bulk capacitor gets deeply discharged. For security reasons, two diodes can be connected in series.
3 + Cbulk 1 2 3 4 8 7 6 5 D3 1N4007 1+ CVCC
Figure 36. A simple resistor in series avoids any latchup in the controller
Figure 37. or a diode forces VCC to reach UVLOlow sooner
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NCP1201
ORDERING INFORMATION
Device NCP1201P60 NCP1201P60G NCP1201D60R2 NCP1201D60R2G NCP1201P100 NCP1201P100G NCP1201D100R2 NCP1201D100R2G Package PDIP-8 PDIP-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) PDIP-8 PDIP-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) 2500 Units / Tape & Reel 50 Units / Rail 2500 Units / Tape & Reel 50 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCP1201
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AG
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP1201
PACKAGE DIMENSIONS
8 LEAD PDIP CASE 626-05 ISSUE L
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
8
5
-B-
1 4
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M TA
M
H
G 0.13 (0.005) B
M
The product described herein (NCP1201), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP1201/D

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